Dynamic Random Access Memory (DRAM) is utilized in modern computing architectures. DRAM may provide advantages of structural simplicity, high speed and low cost in comparison to alternative types of memory.
DRAM commonly utilizes memory cells having one capacitor in combination with a transistor (so-called 1T-1C memory cells), with the capacitor being coupled with a source/drain region of the transistor. One of the limitations to scalability of present 1T-1C configurations is that it is proving difficult to incorporate capacitors having sufficiently high capacitance into highly-integrated architectures.
As another DRAM cell, a 2T-1C memory cell configuration is schematically illustrated in FIG. 1 according to the prior art. The 2T-1C memory cell includes two transistors and one capacitor; with the two transistors of the FIG. 1 configuration being labeled as T1 and T2, and with the capacitor being labeled as CAP.
A source/drain region of T1 connects with a first node of the capacitor (CAP), and the other source/drain region of T1 connects with a first comparative bitline (BL-1). A gate of T1 connects with a wordline (WL). A source/drain region of T2 connects with a second node of the capacitor (CAP), and the other source/drain region of T2 connects with a second comparative bitline BL-2. A gate of T2 connects with the wordline (WL).
The comparative bitlines BL-1 and BL-2 extend to circuitry 4 (e.g., a sense amplifier) which compares electrical properties (e.g., voltage) of the two to ascertain a memory state of memory cell 2.
The 2T-1C configuration of FIG. 1 may be utilized in DRAM and/or other types of memory. The 2T-1C configuration may be advantageous relative to the 1T-1C configuration, in that the 2T-1C configuration may provide improved signal-to-noise, reduced leakage, lower power operation, lower voltage operation, etc.
In some applications, it would be desirable to develop memory array architecture designed to incorporate 2T-1C configurations instead of conventional 1T-1C configurations.